Queued port data controller for microprocessor-based engine control applications
US6427180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1999 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.