SRAM controller for parallel processor architecture including address and command queue and arbiter
US6427196B1 · kind B1 · utility
114Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.