Multiple changeable addressing mapping circuit
US6427200B1 · kind B1 · utility
11Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple changeable addressing mapping circuit is disclosed for converting an input logic address of a field array in a data array into an output physical address. The circuit has multiple address mappers for process the conversion between the input logical address and the output physical address. The circuit also has a mapper selector for selecting an address mapper to output physical address. The circuit further has a control and interface circuit for setting the registers in the address mapper, and controlling the address mapper and mapper selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.