Method for forming wiring pattern of a semiconductor integrated circuit
US6429031B2 · kind B2 · utility
0Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for connecting wiring patterns of an integrated circuit device. A wiring pattern of a semiconductor integrated circuit includes a first line for conducting a first potential and a second line for conducting a second potential. The method detects a portion of a distal end of the first line that overlaps a distal end of the second line and generates an avoidance pattern by eliminating the overlapping portion from the first line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.