Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory

US6429081B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Kelvin Doong · Hsinchu, TW
• Ching-Hsiang Hsu · Hsinchu, TW

Key dates

• Filing date: May 17, 2001
• Grant date: Aug 6, 2002
• Expiry date: May 17, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2211/5641

Abstract

A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel. A control gate comprises a second conductive layer overlying the floating gate with an interlevel dielectric layer therebetween. A parasitic surface transfer-transistor (PASTT) gate comprises the second conductive layer overlying the parasitic channel with the interlevel dielectric layer therebetween…