Semiconductor device having high breakdown voltage and method for manufacturing the device
US6429501B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/112
Abstract
A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P−-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N+-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 1015-1016 atoms/cm3 where it contacts the semiconductive film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.