High speed data sampling with reduced metastability
US6429692B1 · kind B1 · utility
43Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.