Reference signal switchover clock output controller
US6429707B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0994
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.