Method for bias rail buffering
US6429744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45937
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.