Standardized test board for testing custom chips
US6430047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1999 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1394
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed wiring board provides connection between a chip and a standard footprint layout of a test machine. An insulating substrate defines a chip receiving region having a plurality of chip connector pads on one side of the substrate for connection to bump contacts of custom integrated circuit chips. A plurality of layout connectors are in a layout connection region of the board and arranged in the standard footprint layout. Circuit traces provide electrical connection between the chip connectors and the layout connectors, and a solder stop on the substrate extends over the circuit traces between the chip receiving region and the layout connection region. A plurality of plated apertures extend through the substrate in the chip receiving region to a thermally conductive heat sink opposite the chip connectors. In use, a chip is mounted to the board in the chip receiving region and connected to the chip connectors to rigidly mount the chip to the board. A thermally conductive paste extends through the apertures to thermally connect the chip to the heat sink. The solder stop prevents solder connecting the chip to the chip connectors from wicking along the traces thereby preventing de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.