Voltage multiplier for low voltage microprocessor
US6430067B1 · kind B1 · utility
2Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/073
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a voltage multiplier is disclosed that includes a first stage for receiving an input voltage and a first control signal; inverting the first control signal to produce a second control signal; and outputting a first output voltage and the second control signal. The voltage multiplier also includes a second stage for receiving the first output voltage and the second control signal; and outputting a third output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.