Unified table for L2, L3, L4, switching and filtering
US6430188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network switch for network communications, wherein the network switch includes at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate. The at least one data port interface includes an ingress logic circuit in communication with the at least one data port interface for generating at least one of an ingress address resolution and a filtering search request. A CPU interface is provided and configured to communicate with a CPU. A shared hierarchical memory structure including an internal memory in communication with the at least one data port interface, and an external memory in communication with a memory management unit via an external memory interface is provided. A communication channel is provided for communicating data between the at least one data port interface, the internal memory, the CPU interface, and the memory management unit. Additionally, a unified table is provided, wherein the unified table is in connection with the communication channel, and the at least one data port interface. The unified table contains packet handling data for the network switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.