Method and apparatus for reducing direct memory access transfers using smart coalescing
US6430628B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention comprises a method and apparatus for managing data transfers from memory to an input/output device where the data is stored in memory as data fragments. A first list of memory locations for the fragments is received. A sub-set of fragments for copying to at least one of a first and second buffer is selected based on fragment size. A request to copy the selected sub-set of fragments to the at least one first and second buffer is sent. A request to lock down any unselected fragments is sent. A second list of memory locations for the fragments is created. The second list comprises memory locations for the at least one first and second buffer and locked down fragments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.