Linked list memory and method therefor
US6430666B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A linked list memory (8) having an address generator (19) used during initial processing and a method for assigning addresses to lists corresponding to devices using a common memory (10). When the address generator (19) has assigned each address location once, a free list is used to track available addresses. The free list is not used until all addresses have been assigned once. In one embodiment, a counter (22) is incremented each time an address is assigned, where the value of counter (22) provides the address for a write operation. The counter (22) is not effected by requests to read from memory. The free list is not used until the counter (22) has been used to assign all addresses in the memory (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.