Hardware system for fetching mapped branch target instructions of optimized code placed into a trace memory
US6430675B1 · kind B1 · utility
10Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive mechanism uses a cache table to map branch targets. When a fetch instruction is initiated, the inventive mechanism searches the IP-to-TM cache to determine whether the branch target instruction has been optimized and placed into the trace memory. If there is a match with the P-to-TM cache, then the code in the trace is executed. This cache is examined in parallel with Instruction Translation Lookup Buffer (ITLB). If not a match is found in the IP-to-TM cache, the original binary in the physical address provided by the ITLB will be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.