Pre-arbitrated bypasssing in a speculative execution microprocessor
US6430679B1 · kind B1 · utility
10Cited by
11References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.