Processor and method of prefetching data based upon a detected stride
US6430680B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.