Apparatus and method for independent threshold voltage control of memory cell and select gate in a split-EEPROM
US6432761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A split-gate p-channel memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a memory transistor and select transistor that share a common gate. It further includes two independent and distinct threshold voltage adjusts implanted in different portions of a channel region of a substrate of the memory cell. One of the threshold voltage adjusts is disposed in relation to the memory transistor so as to influence its threshold voltage. The other threshold voltage adjust is disposed in relation to the selected transistor so as to influence its threshold voltage. In the method of fabrication, an n-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the memory transistor and a p-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the select transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.