High impedance mirror scheme with enhanced compliance voltage
US6433528B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A high-impedance current source 100 having an enhanced compliance voltage. The current source 100 preferably has a means for generating a biasing current 105 and a first current mirror stage having a first transistor M6 coupled to a second transistor M1. A second current mirror stage having a third transistor M2 coupled to a fourth transistor M5 acts as a feedback circuit. A stabilization circuit having a fifth transistor M3 coupled to a sixth transistor M4 are also included. The stabilization circuit is coupled between the first and second current mirror stages and an output circuit having a seventh transistor M7 is connected to the stabilization circuit between the first and second current mirror stages. The current mirror circuit has a low compliance voltage, enhanced operating characteristics and enhanced dynamics which eliminate the need for OTAs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.