Massive parallel semiconductor manufacturing test process
US6433568B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Aug 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a plurality of integrated circuits each having a processing unit and an electrically programmable memory portion. The method includes providing a temperature cycling unit; inserting the plurality of integrated circuits in the temperature cycling unit; cycling the temperature in the temperature cycling unit through substantially room temperature, a first hot temperature, and a first cold temperature; performing a memory test protocol on the plurality of integrated circuits during the temperature cycling; removing the plurality of integrated circuits from the temperature cycling unit; providing an integrated circuit testing system which includes one or more testers; inserting a first relatively small number of the plurality of integrated circuits into one of the one or more testers; and performing a processor test protocol on the first relatively small number of integrated circuits at a temperature selected from substantially room temperature, a second hot temperature, and a second cold temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.