Heterogeneous programmable gate array
US6433578B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A heterogeneous programmable gate array has an unstructured logic sub-array and a structured logic sub-array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic sub-array. A control signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver structured source signals therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.