Correlated double sampling circuit with op amp
US6433632B1 · kind B1 · utility
17Cited by
9References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/70
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.