Analog-digital converter with single-ended input
US6433724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Mar 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.