Dual fragment-cache pixel processing circuit and method therefore
US6433788B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame. The render backend block combines fragments received from the first and second caches with portions of the current pixel information in the frame buffer to produce revised pixel information that is stored back in the frame buffer. The combination operations performed by the render backend block utilize the state information stored in one of the first and second sets of state…
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