Nonvolatile memory devices having alternative programming
US6434052B1 · kind B1 · utility
3Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is a nonvolatile memory device operable in a plurality of programming cycles, including, a memory cell array formed of a plurality of memory cells connected to bit lines and word lines, a plurality of data buffers for receiving a plurality of data bits, a plurality of write drive circuits disposed between the memory cell array and the data buffers, and a circuit for generating a plurality of selection signals for controlling the write drive circuits, in response to a current level of a power supply voltage. The selection signals determines the number of data bits programmed in one of the programming cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.