Full-duplex speakerphone circuit including a double-talk detector
US6434110B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1998 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Mar 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M9/082
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A communication integrated circuit, such as a full-duplex speakerphone circuit, includes a double-talk detector that operates in combination with an echo canceller. The echo canceller includes an adaptive filter with filter coefficients that are regularly adjusted to train to a received echo. The double-talk detector includes an ERLE detector for measuring the current ERLE of the echo canceller and a logic circuit for determining a best ERLE value over a plurality of measurements. The double-talk detector also includes a power estimator and noise estimator for determining a noise level. The noise level attained when the ERLE value is the best ERLE value is saved as a benchmark noise level. Filter coefficients of the echo canceller are updated or updating is blocked based on several considerations including a comparison of ERLE value to best ERLE value, the noise level in comparison to the benchmark noise level, whether the circuit is operating in half-duplex or full-duplex mode, and detection of a tone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.