Flexible accumulator register file for use in high performance microprocessors
US6434584B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.