Computationally efficient modular multiplication method and apparatus
US6434585B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computationally efficient multiplication method and apparatus for modular exponentiation. The apparatus uses a preload register, coupled to a multiplier at a second input port via a KN bit bus to load the value of the “a” multiplicand in the multiplier in a single clock pulse. The “b” multiplicand (which is also KN bits long) is supplied to the multiplier N bits at a time from a memory output port via an N bit bus coupled to a multiplier first input port. The multiplier multiplies the N bits of the “b” multiplicand by the KN bits of the “a” multiplicand and provides that product at a multiplier output N bits at a time, where it can be supplied to the memory via a memory input port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.