FIFO with random re-read support and its application
US6434676B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO storage structure is provided with a RAM array including a number of memory locations, and control circuitry coupled to the RAM array. The control circuitry facilitates sequential write and read accesses of the memory locations, as well as non-sequential re-read of previously read memory locations. The control circuitry includes in particular circuit elements for facilitating variably deferred release and reclaiming of sequentially read in-use ones of the memory locations, thereby allowing the non-sequential re-reads to be performed in addition to the fundamentally sequential writes and reads. In each of a number of applications, a look up engine is provided with the enhanced FIFO. In one particular application, a forwarding section of a networking device is provided with such look up engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.