Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions
US6434690B1 · kind B1 · utility
21Cited by
8References
29Claims
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Key dates
| Filing date | Jan 11, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.