Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags
US6434691B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 3, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Apr 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.