Encryption processor with shared memory interconnect
US6434699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.