Methods for improving the efficiency of clock gating within low power clock trees
US6434704B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods are provided for improving the efficiency of clock gating within low power clock trees. In a first aspect, a correlation level between a plurality of clock gating signals and their corresponding gates which gate a source clock is determined. The clock gating signals and their corresponding gates are combined into a single clock gating signal and a single corresponding gate if a preselected level of correlation exists therebetween. In a second aspect, an area overlap is determined for a plurality of sinks, and one of the gated drovers of the sinks is removed. The sinks of the removed gated driver then are connected to a remaining gated driver driven by a single clock gating signal and a single corresponding gate. In a third aspect, physically proximate sink clusters are rewired to generate a pure clock gating group within each sink cluster if rewiring the clusters increases wiring length by less than a predetermined amount. In a fourth aspect, a clock gating group is selected and the power dissipation is computed for all sinks within the selected group assuming all the sinks therein are wired without clock gating. The power dissipation also is computed assuming all the sinks…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.