Automated placement of signal distribution to diminish skew among same capacitance targets in integrated circuits
US6434731B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas. Thus, skew is minimized during the automated placement of the design of the signal distribution network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.