Semiconductor integrated circuit device
US6436741B2 · kind B2 · utility
27Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Apr 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.