Self-aligned dual-base semiconductor process and structure incorporating multiple bipolar device types
US6437421B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | May 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques. Since the two base implants for each high-voltage transistor are self-aligned to a single opening through the dielectric layer, excellent control and repeatability is achieved for the high-voltage transistors. Moreover, since the second base implant is common to both types of transistors…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.