CSP stacking technology using rigid/flex construction
US6437433B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Mar 24, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Mar 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable integrated circuit chip package comprising an interconnect sub-assembly which includes an interconnect substrate having first, second and third conductive pad arrays disposed thereon. The interconnect sub-assembly also includes a first rail member which is attached to the interconnect substrate and has a fourth conductive pad array disposed thereon, and a second rail member which is also attached to the interconnect substrate and has a fifth conductive pad array disposed thereon. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate. In addition to the interconnect sub-assembly, the chip package of the present invention includes an integrated circuit chip which is electrically connected to the first conductive pad array of the interconnect substrate of the interconnect sub-assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.