Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6437441B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 1998 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jul 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.