Method for delay line linearity testing
US6437553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jan 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a “COMPARE” value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.