Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure
US6437613B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generating circuit for compensating for a delay difference using a closed loop analog synchronous mirror delay structure is provided. The clock generating circuit divides a delay clock signal and a reference clock signal to generate first and second divided signals, and synchronizes an internal clock signal with the reference clock signal using the first and the second divided signals, at the initial stage of an operation. After predetermined clock cycles, the clock generating circuit divides the internal clock signal to generate the first and the second divided signals. The quick synchronization of the internal clock signal with the reference clock obviates any error which may occur between the delay time of a mirror delay circuit and the delay time of an actual circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.