Delay locked loop incorporating a ring type delay and counting elements
US6437618B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input unit for receiving an external clock signal from which a clock input signal is created; a delay monitor for receiving a clock output signal to monitor a time delay introduced on the clock input signal; and a phase detection unit for receiving the clock input signal and an output of the delay monitor for determining a difference in phase between the clock input and output signals to produce a shift control signal. A shift register for controlling the adjustment of the time delay and a delay line for adjusting the time delay are also provided in the delay locked loop. Both the shift register and the delay line have a ring configuration on their outputs. The delay locked loop provided also includes a first and a second counter for counting the number of data signals outputted from the delay line and the shift register, respectively; a comparator for comparing these counted numbers; and an output unit for receiving the output of the delay line and the compared value to produce the clock outpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.