Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory
US6437619B2 · kind B2 · utility
63Cited by
3References
11Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 13, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.