Current mirror compensation system for power amplifiers
US6437647B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jan 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/302
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two compensating resistors in a mirror bias circuit coupled to a radio frequency (RF) amplifier are configured such that transistor base-emitter voltages are adjusted to stabilize RF transistor quiescent current for variations in collector voltage, Vcc. For example, when battery power is drained during device use, Vcc decreases. As Vcc decreases, less current is drawn through the compensating resistors, thereby decreasing the voltage drop across the compensating resistors and increasing the transistor base-emitter voltages in the mirror bias circuit and the radio frequency (RF) amplifier. Thus, the tendency of the RF transistor quiescent current to decrease as Vcc decreases is off-set because the compensating resistors cause an increase in the RF transistor base-emitter voltage, thereby increasing quiescent current. In one embodiment, the first compensating resistor size is equal to the second compensating resistor size multiplied by the ratio of the buffer transistor current rating to the mirror transistor current rating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.