Phase-locked loop or delay-locked loop circuitry for programmable logic devices
US6437650B1 · kind B1 · utility
44Cited by
30References
23Claims
0Family size
Assignee
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Key dates
| Filing date | May 15, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0997
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.