Method of increasing bus performance to reduce signal propagation delay and achieve incident wave switching
US6437660B1 · kind B1 · utility
3Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09254
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a backplane interconnect configuration for use in a high-speed data processing system, a plurality of connector slots include an array of connector terminals. First conductive traces electrically couple at least two terminals of adjacent slots, the terminals being coupled by the first conductive traces to form multiple clusters. Each of the plurality of the clusters are in turn electrically coupled by separate conductive traces to at least one common node. This configuration allows for a reduction in the propagation delay of signals propagating between connector slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.