Multi-level cache controller
US6437789B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Feb 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accessing a cache memory of a computer graphics system, the apparatus including a frame buffer memory having a graphics memory for storing pixel data for ultimate supply to a video display device, a read cache memory for storing data received from the graphics memory, and a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory. Also included is a frame buffer controller for controlling access to the graphics memory and read and write cache memories. The frame buffer controller includes a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.