Dynamic random access memory with low power consumption
US6438061B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jul 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.