Method and apparatus for margining error rate of multi-drop data buses
US6438159B1 · kind B1 · utility
26Cited by
4References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for optimizing data transfer over a terminated low voltage differential bus includes controlling parameters of a bus driver, a bus bias cancellation circuit, and other bus operating parameters, in response to received test results derived from test patterns sent over the bus at various transfer rates and parameter settings until optimized parameter settings within an acceptable error margin and at a highest available transfer rate are determined between a particular sending unit and a particular receiving unit on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.