System and method for data pacing
US6438628B1 · kind B1 · utility
37Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.