Correlated address prediction
US6438673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.